1. Field of the Invention
The field of the invention is data processing, or, more specifically, leakage tolerant delay locked loop (DLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using leakage tolerant DLL circuit devices.
2. Description of Related Art
A delay locked loop (DLL) circuit device is a control system that generates one or more output signals whose phase is delayed and locked relative to a phase of an input reference signal. For further explanation, FIG. 1 sets forth a diagram of a DLL circuit device found in the prior art. In the DLL circuit device of FIG. 1, the phase difference between a reference signal (118) and a feedback signal (128) is translated by a phase detector (102) into two signals, increase delay signal (120) and decrease delay signal (122). The two signals (120, 122) control a charge pump (104) that steers current into or out of a filter capacitor (106) via a filter control signal (124), causing the voltage across the filter capacitor (106) to increase or decrease. In each cycle, the time during which the charge pump (104) is turned-on is proportional to the phase difference between the reference signal (118) and the feedback signal (128). Hence, the charge delivered by the charge pump (104) is also dependent on the phase difference. The voltage on the filter capacitor (106) is used to control voltage controlled buffers (VCB) (108), which increase or decrease the delay of phases of the output phase signals (130) and the feedback signal (128) relative to a phase of the reference signal (118). That is, the filter capacitor (106) is instrumental in controlling how efficiently the VCB (108) and the DLL circuit device, as a whole, is able to delay the phases of the output phase signals (130) relative to the phase of the reference signal (118).
In an effort to control costs or reduce the size of the components with DLL circuit devices, manufacturers may select a filter capacitor with poor leakage characteristics. A leaky filter capacitor may discharge some of its charge during the operation of the DLL circuit device. Because a DLL circuit device relies on the charge of its filter capacitor to indicate to a VCB an amount to delay phases of output phase signals and a feedback signal, a leaky filter capacitor may cause the VCB to not delay the output phase signals and the feedback signal by the phase difference determined by the phase detector. That is, a leaky filter capacitor could increase the number of frequency cycles that the DLL circuit device must operate to delay and lock the phases of the output phase signals to a phase of a reference signal. In some instances, the degree of leakage in the filter capacitor may prevent a DLL circuit device from completely phase locking the output phase signals to the reference signal.
For further explanation, FIG. 2 sets forth a diagram illustrating a transient response of the DLL circuit device of FIG. 1, configured with a leaky filter capacitor. As explained above, the goal of a DLL circuit device is to delay and lock phases of output phase signals and a feedback signal relative to a phase of a reference signal. For example, the DLL circuit device of FIG. 1 may be programmed to delay and lock the feedback signal (128) by three hundred and sixty degrees relative to the reference signal (118).
The transient response of FIG. 2 illustrates the reference signal (118) and the feedback signal (128) at multiple time points (250-257) over time (290). At the time point (250), the feedback signal (128) is delayed relative to the reference signal (118) but there is still a phase difference between the two signals (118, 128). That is, the rising edge of the feedback signal (128) begins at the time point (250) and the next rising edge of the reference signal (118) begins at the time point (251). In response to detecting this difference between the two signals (118, 128), the phase detector (102) generates the increase delay signal (120) during the two time points (250, 251) and the charge pump provides a corresponding charge to the filter capacitor (106). During the time points (250, 251), the VCB control signal (126) is generated that corresponds to the charge of the filter capacitor (106). However, between the time point (251) and the time point (252), the increase delay error signal (120) is not generated and the charge pump (104) does not continue to charge the filter capacitor (106). In the example of FIGS. 1-2, the reference plate of the filter capacitor (106) is coupled to a low potential or ground, hence leakage in the filter capacitor (106) occurs in that direction. Because the filter capacitor (106) is leaky, the filter capacitor (106) begins to discharge and thus the VCB control signal (126) begins to decrease. In fact, at the time point (252), the filter capacitor (306) is at substantially the same charge it was at before the time point (250). As a consequence of the filter capacitor (306) discharging, the delay of the feedback signal (128) is not increased and the same increase delay signal (120) is generated between time points (252-257). That is, the leakage in the filter capacitor (106) prevents the DLL circuit device of FIG. 1 from completing the delay and locking of the phases of the phase output signals (130) and the feedback signal (128) to a phase of the reference signal (118).